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HT36A4 Music Synthesizer 8-Bit MCU
Technical Document
* Tools Information * FAQs * Application Note
Features
* Operating voltage: 2.4V~5.0V * Operating frequency: 3.58MHz~12MHz (typ. 8MHz) * 8 bidirectional I/O lines * Two 8-bit programmable timer with 8 stage prescaler * Watchdog Timer * Built-in 8-bit MCU with 2088 bits RAM * Built-in 32K16-bit ROM for program/data shared * Mono output * High D/A converter resolution: 16 bits * Polyphonic up to 8 notes * Independent volume mix can be assigned to each * Sampling rate of 25kHz as 6.4MHz for system
frequency
* Eight-level subroutine nesting * HALT function and wake-up feature to reduce power
consumption
* Bit manipulation instructions * 16-bit table read instructions * 63 powerful instructions * All instructions in 1 or 2 machine cycles * 16-pin DIP/SOP package
sound component
General Description
The HT36A4 is an 8-bit high performance RISC-like microcontroller specifically designed for music applications. It provides an 8-bit MCU and a 8 channel wavetable synthesizer. The program ROM is composed of both program control codes and wavetable voice codes, and can be easily programmed. The HT36A4 has a built-in 8-bit microprocessor which programs the synthesizer to generate the melody by setting the special register from 20H~2AH. A HALT feature is provided to reduce power consumption.
Block Diagram
3 2 K 1 6 - b it ROM 8 - B it MCU 2088 RAM M u ltip lie r /P h a s e G e n e ra l 1 6 - B it DAC
PA0~PA7
OSC1 OSC2 RES
VD VS VD VS S
D DA SA
AUD
Rev. 1.10
1
March 12, 2007
HT36A4
Pin Assignment
PA4 1 2 3 4 5 6 7 8 PA5 PA6 PA7 VSS VDD VDDA TEST 16 15 14 13 12 11 10 9 PA3 PA2 PA1 PA0 OSC2 OSC1 RES AUD
H T36A 4 1 6 D IP -A /S O P -A
Pad Assignment
PA5 PA6
1 2 17
PA4
16
PA3
15
PA2
14 13 12
PA1 PA0
PA7
(0 , 0 )
11
OSC2
VSS
3 4
VSSA VDD VDDA
5 6 7 8 10 9
OSC1 RES
TEST
AUD
Chip size: 2140 2560 (mm)2 * The IC substrate should be connected to VSS in the PCB layout artwork.
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2
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HT36A4
Pad Coordinates
Pad No. 1 2 3 4 5 6 7 8 9 X -903.425 -903.425 -882.900 -882.900 -831.950 -831.950 -177.390 -65.590 900.650 Y 1096.250 985.650 -650.050 -776.910 -886.910 -1025.350 -1045.600 -1045.600 -1107.950 Pad No. 10 11 12 13 14 15 16 17 X 900.650 900.650 901.625 901.625 697.050 586.450 -588.250 -698.850 Y -994.626 -316.774 1006.000 1116.600 1114.025 1114.025 1114.025 1114.025 Unit: mm
Pad Description
Pad Name PA0~PA7 VSSA VSS VDD VDDA TEST AUD RES OSC1 OSC2 I/O I/O 3/4 3/4 3/4 3/4 3/4 O I I O Internal Connection Pull-High or None 3/4 3/4 3/4 3/4 3/4 3/4 3/4 Function Bidirectional 8-bit Input/Output port, wake-up by mask option Negative power supply of DAC, ground Negative power supply, ground Positive power supply DAC power supply No connection (open) Audio output for driving a external transistor or for driving HT82V733 Reset input, active low OSC1 and OSC2 are connected to an RC network or a crystal (by mask option) for the internal system clock. In the case of RC operation, OSC2 is the output terminal for 1/4 system clock (fOSC2=fOSC/8). The system clock may come from the crystal, the two pins cannot be floating.
3/4
Absolute Maximum Ratings
Supply Voltage ......................... VSS-0.3V to VSS+5.5V Input Voltage ............................ VSS-0.3V to VDD+0.3V Storage Temperature .......................... -50C to 125C Operating Temperature ....................... -40C to 85C*
Note: These are stress ratings only. Stresses exceeding the range specified under Absolute Maximum Ratings may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. * ROSC=Metal resistor or crystal
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HT36A4
D.C. Characteristics
Symbol VDD IDD ISTB IOL IOH IO RPH VIH1 VIL1 VIH2 VIL2 Parameter Operating Voltage Operating Current Standby Current (WDT Disabled) I/O Ports Sink Current I/O Ports Source Current AUD Source Current Pull-High Resistance of I/O Ports Input High Voltage for I/O Ports Input Low Voltage for I/O Ports Input High Voltage (RES) Input Low Voltage (RES) Test Conditions VDD 3/4 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V Conditions 3/4 No load, fOSC=8MHz No load, System HALT VOL=0.5V VOH=4.5V VOH=4.5V VIL=0V 3/4 3/4 3/4 3/4 Min. 2.4 3/4 3/4 9.7 -5.2 3/4 11 3.5 0 3/4 3/4 Typ. 3 8 1 16.2 -8.7 -5 22 3/4 3/4 4 2.5 Max. 5 16 3/4 3/4 3/4 3/4 44 5 1.5 3/4 3/4 Ta=25C Unit V mA mA mA mA mA kW V V V V
A.C. Characteristics
Symbol MCU Interface fOSC fSYS tWDT tRES System Frequency System Clock Watchdog Time-Out Period (RC) External Reset Low Pulse Width 5V 5V 3/4 3/4 8MHz crystal 3/4 Without WDT prescaler 3/4 3/4 4 9 1 8 3/4 17 3/4 3/4 8 35 3/4 Parameter Test Conditions VDD Conditions Min. Typ. Max.
Ta=25C Unit
MHz MHz ms ms
Rev. 1.10
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March 12, 2007
HT36A4
Characteristics Curves
V vs F Characteristics Curve
H T 3 6 A 4 V v s . F C h a r t (F o r 3 .0 V )
10
9
8 F re q u e n c y (M H z )
1 5 5 k W /8 M H z 7
6 2 0 0 k W /6 M H z 5
4
2 .4
2 .6
2 .8
3
3 .2
3 .4
3 .6 V
DD
3 .8 (V )
4
4 .2
4 .4
4 .6
4 .8
5
10
H T 3 6 A 4 V v s . F C h a r t (F o r 4 .5 V )
9
8 F re q u e n c y (M H z )
1 4 5 k W /8 M H z
7
6 1 9 0 k W /6 M H z
5
4 2 .4 2 .6 2 .8 3 3 .2 3 .4 3 .6 V
DD
3 .8 (V )
4
4 .2
4 .4
4 .6
4 .8
5
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HT36A4
R vs F Characteristics Curve
H T36A 4 R v s . F C h a rt
14
12
10 F re q u e n c y (M H z ) 8 6
4
3 .0 V 4 .5 V
2
120
150
180
200 R (k W )
220
240
270
300
Function Description
Execution Flow The system clock for the HT36A4 is derived from either a crystal or an RC oscillator. The oscillator frequency divided by 2 is the system clock for the MCU (fOSC=fSYS2) and it is internally divided into four non-overlapping clocks. One instruction cycle consists of four system clock cycles. Instruction fetching and execution are pipelined in such a way that a fetch takes one instruction cycle while decoding and execution takes the next instruction cycle. However, the pipelining scheme causes each instruction to effectively execute in one cycle. If an instruction changes the program counter, two cycles are required to complete the instruction. Program Counter - PC The 13-bit program counter (PC) controls the sequence in which the instructions stored in program ROM are executed and its contents specify a maximum of 8192 addresses for each bank. After accessing a program memory word to fetch an instruction code, the contents of the program counter are incremented by one. The program counter then points to the memory word containing the next instruction code. When executing a jump instruction, conditional skip execution, loading PCL register, subroutine call, initial reset, internal interrupt, external interrupt or return from subroutine, the PC manipulates the program transfer by loading the address corresponding to each instruction. The conditional skip is activated by instruction. Once the condition is met, the next instruction, fetched during the current instruction execution, is discarded and a dummy cycle replaces it to retrieve the proper instruction. Otherwise proceed with the next instruction. The lower byte of the program counter (PCL) is a readable and writeable register (06H). Moving data into the PCL performs a short jump. The destination will be
T1 T2 T3 T4 T1 T2 T3 T4
S y s te m
C lo c k o f M C U (fO S C /2 ) PC
T1
T2
T3
T4
PC
PC+1
PC+2
F e tc h IN S T (P C ) E x e c u te IN S T (P C -1 )
F e tc h IN S T (P C + 1 ) E x e c u te IN S T (P C )
F e tc h IN S T (P C + 2 ) E x e c u te IN S T (P C + 1 )
Execution Flow
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HT36A4
Mode Initial Reset Timer/Event Counter 0 Overflow Timer/Event Counter 1 Overflow Skip Loading PCL Jump, Call Branch Return from Subroutine PF1 PF0 *12 *11 *10 PF1 PF0 #12 #11 #10 Program Counter *14 *13 *12 *11 *10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 *9 0 0 0 *8 0 0 0 *7 0 0 0 *6 0 0 0 *5 0 0 0 *4 0 0 0 *3 0 1 1 *2 0 0 1 *1 0 0 0 *0 0 0 0
Program Counter+2 *9 #9 *8 #8 S8 @7 @6 @5 @4 @3 @2 @1 @0 #7 S7 #6 S6 #5 S5 #4 S4 #3 S3 #2 S2 #1 S1 #0 S0
PF1 PF0 S12 S11 S10 S9 Program Counter
Note:
*12~*0: Bits of Program Counter #12~#0: Bits of Instruction Code @7~@0: Bits of PCL
@7~@0: Bits of PCL S12~S0: Bits of Stack Register PF1~PF0: Bits of Bank Register service program on each bank. If a timer interrupt results from a Timer Counter 1 overflow, and if the interrupt is enabled and the stack is not full, the program begins execution at location 00CH corresponding to its bank.
* Table location
within 256 locations. Once a control transfer takes place, an additional dummy cycle is required. Program ROM HT36A4 provides 15 address lines WA[14:0] to read the Program ROM which is up to 512K bits, and is commonly used for the wavetable voice codes and the program memory. It provides two address types, one type is for program ROM, which is addressed by a bank pointer PF1~0 and a 13-bit program counter PC 12~0; and the other type is for wavetable code, which is addressed by the start address ST10~0. On the program type, WA14~0=PF1~0213+ PC12~0. On the wave table ROM type, WA15~0=ST10~025. Program Memory - ROM The program memory is used to store the program instructions which are to be executed. It also contains data, table, and interrupt entries, and is organized into 819216 bits, addressed by the bank pointer, program counter and table pointer. Certain locations in the program memory of each bank are reserved for special usage:
* Location 000H on bank0
Any location in the ROM space can be used as look-up tables. The instructions TABRDC [m] (the current page, 1 page=256 words) and TABRDL [m] (the last page) transfer the contents of the lower-order byte to the specified data memory, and the higher-order byte to TBLH (08H). Only the destination of the lower-order byte in the table is well-defined, the higher-order byte of the table word are transferred to the TBLH. The Table Higher-order byte register (TBLH) is read only. The Table Pointer (TBLP) is a read/write register (07H), which indicates the table location. Before accessing the table, the location must be placed in TBLP. The TBLH is read only and cannot be restored. If the main routine and the ISR (Interrupt Service Routine) both employ the table read instruction, the contents of the TBLH in the main routine are likely to be changed by the table read instruction used in the ISR. Errors can occur. In this case, using the ta0000H 0008H 000CH D e v ic e in itia liz a tio n p r o g r a m T im e r C o u n te r 0 in te r r u p t s u b r o u tin e T im e r C o u n te r 1 in te r r u p t s u b r o u tin e P ro g ra m ROM
This area is reserved for the initialization program. After chip reset, the program always begins execution at location 000H on bank0.
* Location 008H
n00H nFFH
L o o k - u p ta b le ( 2 5 6 w o r d s )
This area is reserved for the Timer Counter 0 interrupt service program on each bank. If timer interrupt results from a Timer Counter 0 overflow, and if the interrupt is enabled and the stack is not full, the program begins execution at location 008H corresponding to its bank.
* Location 00CH
1FFFH
L o o k - u p ta b le ( 2 5 6 w o r d s ) 1 6 b its N o te : n ra n g e s fro m 0 0 to 1 F .
This area is reserved for the Timer Counter 1 interrupt
Program Memory for Each Bank
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HT36A4
Instruction(s) TABRDC [m] TABRDL [m] Table Location *14 P14 P14 *13 P13 P13 *12 P12 1 *11 P11 1 *10 P10 1 *9 P9 1 *8 P8 1 *7 @7 @7 *6 @6 @6 *5 @5 @5 *4 @4 @4 *3 @3 @3 *2 @2 @2 *1 @1 @1 *0 @0 @0
Table Location Note: *12~*0: Bits of table location P12~P8: Bits of current Program Counter @7~@0: Bits of table pointer P14~P13: Bits of bank PF1~PF0
ble read instruction in the main routine and the ISR simultaneously should be avoided. However, if the table read instruction has to be applied in both the main routine and the ISR, the interrupt should be disabled prior to the table read instruction. It will not be enabled until the TBLH has been backed up. All table related instructions need 2 cycles to complete the operation. These areas may function as normal program memory depending upon user requirements.
* Bank pointer
If the stack is full and a non-masked interrupt takes place, the interrupt request flag will be recorded but the acknowledgment will be inhibited. When the stack pointer is decremented (by RET or RETI), the interrupt will be serviced. This feature prevents stack overflow allowing the programmer to use the structure more easily. In a similar case, if the stack is full and a CALL is subsequently executed, a stack overflow occurs and the first entry will be lost (only the most recent eight return address are stored). Data Memory - RAM The data memory is designed with 2568 bits. The data memory is divided into three functional groups: special function registers, wavetable function register, and general purpose data memory (2088). Most of them are read/write, but some are read only. The unused space before 30H is reserved for future expanded usage and reading these locations will return the result 00H. The general purpose data memory, addressed from 30H to FFH, is used for data and control information under instruction command. All data memory areas can handle arithmetic, logic, increment, decrement and rotate operations directly. Except for some dedicated bits, each bit in the data memory can be set and reset by the SET [m].i and CLR [m].i instructions, respectively. They are also indirectly accessible through Memory pointer registers (MP0:01H, MP1:03H). Indirect Addressing Register Location 00H and 02H are indirect addressing registers that are not physically implemented. Any read/write operation of [00H] and [02H] access data memory pointed to by MP0 (01H) and MP1 (03H) respectively. Reading location 00H or 02H directly will return the result 00H. And writing directly results in no operation. The function of data movement between two indirect addressing registers, is not supported. The memory pointer registers, MP0 and MP1, are 8-bit register which can be used to access the data memory by combining corresponding indirect addressing registers.
The program memory is organized into 4 banks and each bank into 819216 bits of program ROM. PF[1~0] is bank pointer. After an instruction has been executed to write data to the PF register to select a different bank, note that the new bank will not be selected immediately. It is not until the following instruction has completed execution that the bank will be actually selected. It should be note that the PF register is write only. Wavetable ROM The ST[10~0] is used to defined the start address of each sample on the wavetable and read the waveform data from the location. HT36A4 provides 16 output address lines from WA[15~0], the ST[10~0] is used to locate the major 16 bits i.e. WA[15~5] and the undefined data from WA[4~0] is always set to 00000b. So the start address of each sample have to be located at a multiple of 32. Otherwise, the sample will not be read out correctly because it has a wrong starting code. Stack Register - Stack This is a special part of the memory which is used to save the contents of the program counter (PC) only. The stack is organized into 8 levels and is neither part of the data nor part of the program space, and is neither readable nor writeable. The activated level is indexed by the stack pointer (SP) and is neither readable nor writeable. At a subroutine call or interrupt acknowledgment, the contents of the program counter are pushed onto the stack. At the end of a subroutine or an interrupt routine, signaled by a return instruction (RET or RETI), the program counter is restored to its previous value from the stack. After a chip reset, the stack pointer will point to the top of the stack.
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HT36A4
00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH V o lu m e C o n tr o l L o w ( V o lL ) DAC DAC D AC Low PF H ig h B y te ( D A H ) B y te (D A L ) C o n tro l (D A C ) TM R1L TM R1C PA PAC TM R0L TM R0C S p e c ia l P u r p o s e D a ta M e m ro y ACC PCL TBLP TBLH W DTS STATUS IN T C In d ir e c t A d d r e s s in g R e g is te r 0 MP0 In d ir e c t A d d r e s s in g R e g is te r 1 MP1
Arithmetic and Logic Unit - ALU This circuit performs 8-bit arithmetic and logic operation. The ALU provides the following functions:
* Arithmetic operations (ADD, ADC, SUB, SBC, DAA) * Logic operations (AND, OR, XOR, CPL) * Rotation (RL, RR, RLC, RRC) * Increment & Decrement (INC, DEC) * Branch decision (SZ, SNZ, SIZ, SDZ ....)
The ALU not only saves the results of a data operation but can also change the status register. Status Register - STATUS This 8-bit register (0AH) contains the zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), power down flag (PDF) and Watchdog time-out flag (TO). It also records the status information and controls the operation sequence. With the exception of the TO and PDF flags, bits in the status register can be altered by instructions like any other register. Any data written into the status register will not change the TO or PDF flags. In addition it should be noted that operations related to the status register may give different results from those intended. The TO and PDF flags can only be changed by system power up, Watchdog Timer overflow, executing the HALT instruction and clearing the Watchdog Timer.
W a v e ta b le F u n c tio n R e g is te r
C h a n n e l N u m b e r S e le c t ( C H A N ) F r e q u e n c y N u m b e r H ig h B y te ( F r e q N H ) F re q u e n c y N u m b e r L o w B y te (F re q N L ) S ta r t A d d r e s s H ig h B y te ( A d d r H ) S ta rt A d d re s s L o w B y te (A d d rL ) R e p e a t N u m b e r H ig h B y te ( R e H ) R e p e a t N u m b e r L o w B y te (R e L ) V o lu m e C o n tr o l H ig h ( V o lH )
The Z, OV, AC and C flags generally reflect the status of the latest operations. In addition, on entering the interrupt sequence or executing a subroutine call, the status register will not be automatically pushed onto the stack. If the contents of status are important and the subroutine can corrupt the status register, the programmer must take precautions to save it properly. Interrupt The HT36A4 provides two internal Timer Counter interrupts on each bank. The Interrupt Control register (INTC;0BH) contains the interrupt control bits that sets the enable/disable and the interrupt request flags. Once an interrupt subroutine is serviced, all other interrupts will be blocked (by clearing the EMI bit). This scheme may prevent any further interrupt nesting. Other interrupt requests may occur during this interval but only the interrupt request flag is recorded. If a certain interrupt needs servicing within the service routine, the programmer may set the EMI bit and the corresponding bit of the INTC to allow interrupt nesting. If the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the Stack Pointer is decremented. If immediate service is desired, the stack must be prevented from becoming full.
2FH 30H G e n e ra l P u rp o s e D a ta M e m o ry (2 0 8 B y te s ) FFH
:U nused. R e a d a s "0 0 "
RAM Mapping
Accumulator The accumulator closely relates to ALU operations. It is mapped to location 05H of the data memory and it can operate with immediate data. The data movement between two data memory locations must pass through the accumulator.
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HT36A4
Bit No. 0 Label C Function C is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise C is cleared. Also it is affected by a rotate through carry instruction. AC is set if an operation results in a carry out of the low nibbles in addition or no borrow from the high nibble into the low nibble in subtraction; otherwise AC is cleared. Z is set if the result of an arithmetic or logical operation is zero; otherwise Z is cleared. OV is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise OV is cleared. PDF is cleared by either a system power-up or executing the CLR WDT instruction. PDF is set by executing the HALT instruction. TO is cleared by a system power-up or executing the CLR WDT or HALT instruction. TO is set by a WDT time-out. Unused bit, read as 0 Status (0AH) Register
1 2 3 4 5 6~7
AC Z OV PDF TO 3/4
All these kinds of interrupt have a wake-up capability. As an interrupt is serviced, a control transfer occurs by pushing the program counter onto the stack and then branching to subroutines at specified locations in the program memory. Only the program counter is pushed onto the stack. If the contents of the register and Status register (STATUS) are altered by the interrupt service program which may corrupt the desired control sequence, then the programmer must save the contents first. The internal Timer Counter 0 interrupt is initialized by setting the Timer Counter 0 interrupt request flag (T0F; bit 5 of INTC), caused by a Timer Counter 0 overflow. When the interrupt is enabled, and the stack is not full and the T0F bit is set, a subroutine call to location 08H will occur. The related interrupt request flag (T0F) will be reset and the EMI bit cleared to disable further interrupts. The Timer Counter 1 interrupt is operated in the same manner as Timer Counter 0. The related interrupt control bits ET1I and T1F of the Timer Counter 1 are bit 3 and bit 6 of the INTC respectively. During the execution of an interrupt subroutine, other interrupt acknowledgments are held until the RETI instruction is executed or the EMI bit and the related interrupt control bit are set to 1 (if the stack is not full). To return from the interrupt subroutine, the RET or RETI instruction may be invoked. RETI will set the EMI bit to enable an interrupt service, but RET will not. Interrupts occurring in the interval between the rising edges of two consecutive T2 pulses, will be serviced on the latter of the two T2 pulses, if the corresponding interrupts are enabled. In the case of simultaneous requests the priorities in the following table apply. These can be masked by resetting the EMI bit.
Interrupt Source Timer Counter 0 overflow Timer Counter 1 overflow
Priority 1 2
Vector 08H 0CH
Once the interrupt request flags (T0F, T1F) are set, they will remain in the INTC register until the interrupts are serviced or cleared by a software instruction. It is recommended that a program does not use the CALL subroutine within the interrupt subroutine. Because interrupts often occur in an unpredictable manner or need to be serviced immediately in some applications, if only one stack is left and enabling the interrupt is not well controlled, once the CALL subroutine operates in the interrupt subroutine, it may damage the original control sequence. Oscillator Configuration The HT36A4 provides two types of oscillator circuit for the system clock, i.e., RC oscillator and crystal oscillator. No matter what type of oscillator, the signal divided by 2 is used for the system clock (fSYS=fOSC/2). The HALT mode stops the system oscillator and ignores external signal to conserve power. If the RC oscillator is used, an external resistor between OSC1 and VSS is required, and the range of the resistance should be from 30kW to 680kW. The system clock, divided by 4 (fOSC2= fSYS/4=fOSC/8), is available on OSC2 with pull-high resistor, which can be used to synchronize external logic. The RC oscillator provides the most cost effective solution. However, the frequency of the oscillation may vary with VDD, temperature, and the chip itself due to process variations. It is therefore, not suitable for timing sensitive operations where accurate oscillator frequency is desired.
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Bit No. 0 1 2 3 4 5 6 7 Label EMI 3/4 ET0I ET1I 3/4 T0F T1F 3/4 Function Controls the Master (Global) interrupt (1=enabled; 0=disabled) Unused bit, read as 0 Controls the Timer Counter 0 interrupt (1=enabled; 0=disabled) Controls the Timer Counter 1 interrupt (1=enabled; 0=disabled) Unused bit, read as 0 Internal Timer Counter 0 request flag (1=active; 0=inactive) Internal Timer Counter 1 request flag (1=active; 0=inactive) Unused bit, read as 0 INTC (0BH) Register
OSC1 V
DD
OSC1
OSC2 C r y s ta l O s c illa to r
fO
SC
/8
RC
OSC2
O s c illa to r
options. This timer is designed to prevent a software malfunction or sequence jumping to an unknown location with unpredictable results. The Watchdog Timer can be disabled by mask option. If the Watchdog Timer is disabled, all the executions related to the WDT result in no operation. Once the internal WDT oscillator (RC oscillator with a period of 78ms normally) is selected, it is first divided by 256 (8-stages) to get the nominal time-out period of approximately 20ms. This time-out period may vary with temperature, VDD and process variations. By invoking the WDT prescaler, longer time-out periods can be realized. Writing data to WS2, WS1, WS0 (bit 2,1,0 of the WDTS) can give different time-out periods. If WS2, WS1, WS0 all equal to 1, the division ratio is up to 1:128, and the maximum time-out period is 2.6 seconds. If the WDT oscillator is disabled, the WDT clock may still come from the instruction clock and operate in the same manner except that in the HALT state the WDT may stop counting and lose its protecting purpose. In this situation the logic can only be restarted by external logic. The high nibble and bit 3 of the WDTS are reserved for user defined flags, and the programmer may use these flags to indicate some specified status.
System Oscillator
On the other hand, if the crystal oscillator is selected, a crystal across OSC1 and OSC2 is needed to provide the feedback and phase shift required for the oscillator, and no other external components are required. A resonator may be connected between OSC1 and OSC2 to replace the crystal and to get a frequency reference, but two external capacitors in OSC1 and OSC2 are required. The WDT oscillator is a free running on-chip RC oscillator, and no external components are required. Even if the system enters the power down mode, the system clock is stopped, but the WDT oscillator still works with a period of approximately 78ms. The WDT oscillator can be disabled by mask option to conserve power. Watchdog Timer - WDT The WDT clock source is implemented by a dedicated RC oscillator (WDT oscillator) or instruction clock (system clock of the MCU divided by 4), determined by mask
fO
SC
/8
M ask O p tio n S e le c t 8 - b it C o u n te r
W D T P r e s c a le r 7 - b it C o u n te r
W DT OSC
8 -to -1 M U X W D T T im e - o u t
W S0~W S2
Watchdog Timer
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March 12, 2007
HT36A4
WS2 0 0 0 0 1 1 1 1 WS1 0 0 1 1 0 0 1 1 WS0 0 1 0 1 0 1 0 1 Division Ratio 1:1 1:2 1:4 1:8 1:16 1:32 1:64 1:128 The system can leave the HALT mode by means of an external reset, an interrupt, an external falling edge signal on port A or a WDT overflow. An external reset causes a device initialization and the WDT overflow performs a warm reset. By examining the TO and PDF flags, the cause for a chip reset can be determined. The PDF flag is cleared when there is a system power-up or by executing the CLR WDT instruction and it is set when a HALT instruction is executed. The TO flag is set if the WDT time-out occurs, and causes a wake-up that only resets the program counter and stack pointer, the others remain in their original status. The port A wake-up and interrupt methods can be considered as a continuation of normal execution. Each bit in port A can be independently selected to wake-up the device by mask option. Awakening from an I/O port stimulus, the program will resume execution of the next instruction. If awakening from an interrupt, two sequences may occur. If the related interrupts is disabled or the interrupts is enabled but the stack is full, the program will resume execution at the next instruction. If the interrupt is enabled and the stack is not full, a regular interrupt response takes place. Once a wake-up event occurs, it takes 1024 tSYS (system clock period) to resume to normal operation. In other words, a dummy cycle period will be inserted after the wake-up. If the wake-up results from an interrupt acknowledge, the actual interrupt subroutine will be delayed by one more cycle. If the wake-up results in next instruction execution, this will execute immediately after a dummy period has finished. If an interrupt request flag is set to 1 before entering the HALT mode, the wake-up function of the related interrupt will be disabled. To minimize power consumption, all I/O pins should be carefully managed before entering the HALT status.
If the device operates in a noisy environment, using the on-chip RC oscillator (WDT OSC) is strongly recommended, since the HALT will stop the system clock. The WDT overflow under normal operation will initialize a chip reset and set the status bit TO. Whereas in the HALT mode, the overflow will initialize a warm reset only the program counter and stack pointer are reset to zero. To clear the WDT contents (including the WDT prescaler), 3 methods are implemented; external reset (a low level to RES), software instructions, or a HALT instruction. The software instructions include CLR WDT and the other set - CLR WDT1 and CLR WDT2. Of these two types of instructions, only one can be active depending on the mask option - CLR WDT times selection option. If the CLR WDT is selected (i.e. CLRWDT times equal one), any execution of the CLR WDT instruction will clear the WDT. In case CLR WDT1 and CLR WDT2 are chosen (i.e. CLRWDT times equal two), these two instructions must be executed to clear the WDT; otherwise, the WDT may reset the chip because of time-out. Power Down Operation - HALT The HALT mode is initialized by a HALT instruction and results in the following...
* The system oscillator will turn off but the WDT oscilla-
tor keeps running (If the WDT oscillator is selected). Watchdog Timer - WDT
* The contents of the on-chip RAM and registers remain
unchanged
* The WDT and WDT prescaler will be cleared and
starts to count again (if the clock comes from the WDT oscillator).
* All I/O ports maintain their original status. * The PDF flag is set and the TO flag is cleared
Rev. 1.10
12
March 12, 2007
HT36A4
Reset There are 3 ways in which a reset can occur:
* RES reset during normal operation * RES reset during HALT * WDT time-out reset during normal operation
The functional units chip reset status are shown below. Program Counter Interrupt Prescaler WDT Timer Counter (0/1) Input/output ports Stack Pointer 000H Disable Clear Clear. After master reset, WDT begins counting Off Input mode Points to the top of stack
The WDT time-out during HALT is different from other chip reset conditions, since it can perform a warm re set that just resets the program counter and stack pointer, leaving the other circuits to maintain their state. Some registers remain unchanged during any other reset conditions. Most registers are reset to the initial condition when the reset conditions are met. By examining the PDF and TO flags, the program can distinguish between different chip resets. TO 0 u 0 1 1 PDF 0 u 1 u 1 RESET Conditions RES reset during power-up RES reset during normal operation RES wake-up HALT WDT time-out during normal operation WDT wake-up HALT
VDD RES S S T T im e - o u t C h ip R e s e t tS
ST
Reset Timing Chart
Note: u stands for unchanged To guarantee that the system oscillator has started and stabilized, the SST (System Start-up Timer) provides an extra-delay of 1024 system clock pulses during system power up or when the system awakes from a HALT state. When a system power-up occurs, the SST delay is added during the reset period. But when the reset comes from the RES pin, the SST delay is disabled. Any wake-up from HALT will enable the SST delay.
V
DD
HALT W DT W DT T im e - o u t R eset
W a rm
R eset
RES SST 1 0 -s ta g e R ip p le C o u n te r P o w e r - o n D e te c tin g C o ld R eset
OSCI
Reset Configuration
RES
Reset Circuit
Rev. 1.10
13
March 12, 2007
HT36A4
The registers status is summarized in the following table: Register MP0 MP1 ACC Program Counter TBLP TBLH WDTS STATUS INTC TMR0L TMR0C TMR1L TMR1C PA PAC PF DAH DAL DAC CHAN FreqNH FreqNL AddrH AddrL ReH ReL VolH VolL Note: Reset (Power On) xxxx xxxx xxxx xxxx xxxx xxxx 0000H xxxx xxxx xxxx xxxx 0000 0111 --00 xxxx -00- 00-0 xxxx xxxx 00-0 1000 xxxx xxxx 00-0 1000 1111 1111 1111 1111 ---- --00 xxxx xxxx xxxx xxxx ---- --00 00-- -000 xxxx xxxx xxxx xxxx ---- -xxx xxxx xxxx x--- --xx xxxx xxxx ---- --xx xxxx xxxx * stands for warm reset u stands for unchanged x stands for unknown - stands for unused WDT Time-out (Normal Operation) uuuu uuuu uuuu uuuu uuuu uuuu 0000H uuuu uuuu uuuu uuuu 0000 0111 --1u uuuu -00- 00-0 xxxx xxxx 00-0 1000 xxxx xxxx 00-0 1000 1111 1111 1111 1111 ---- --00 uuuu uuuu uuuu uuuu ---- --00 uu-- -uuu uuuu uuuu uuuu uuuu ---- -uuu uuuu uuuu u--- --uu uuuu uuuu ---- --uu uuuu uuuu RES Reset (Normal Operation) uuuu uuuu uuuu uuuu uuuu uuuu 0000H uuuu uuuu uuuu uuuu 0000 0111 --uu uuuu -00- 00-0 xxxx xxxx 00-0 1000 xxxx xxxx 00-0 1000 1111 1111 1111 1111 ---- --00 uuuu uuuu uuuu uuuu ---- --00 uu-- -uuu uuuu uuuu uuuu uuuu ---- -uuu uuuu uuuu u--- --uu uuuu uuuu ---- --uu uuuu uuuu RES Reset (HALT) uuuu uuuu uuuu uuuu uuuu uuuu 0000H uuuu uuuu uuuu uuuu 0000 0111 --01 uuuu -00- 00-0 xxxx xxxx 00-0 1000 xxxx xxxx 00-0 1000 1111 1111 1111 1111 ---- --00 uuuu uuuu uuuu uuuu ---- --00 uu-- -uuu uuuu uuuu uuuu uuuu ---- -uuu uuuu uuuu u--- --uu uuuu uuuu ---- --uu uuuu uuuu WDT Time-out (HALT)* uuuu uuuu uuuu uuuu uuuu uuuu 0000H uuuu uuuu uuuu uuuu uuuu uuuu --11 uuuu -uu- uu-u uuuu uuuu uu-u uuuu uuuu uuuu uu-u uuuu uuuu uuuu uuuu uuuu ---- --uu uuuu uuuu uuuu uuuu ---- --uu uu-- -uuu uuuu uuuu uuuu uuuu ---- -uuu uuuu uuuu u--- --uu uuuu uuuu ---- --uu uuuu uuuu
Rev. 1.10
14
March 12, 2007
HT36A4
Timer 0/1 Timer 0 is an 8-bit counter, and its clock source comes from the system clock divided by an 8-stage prescaler. T h e re a r e o n e r egi s t er s r e l at ed t o Ti m e r 0 ; TMR0L(0DH) and TMR0C(0EH). One physical registers are mapped to TMR0L location; writing TMR0L makes the starting value be placed in the Timer 0 preload register and reading the TMR0 gets the contents of the Timer 0 counter. The TMR0C is a control register, which defines the division ration of the prescaler and counting enable or disable. Writing data to B2, B1 and B0 (bits 2, 1, 0 of TMR0C) can yield various clock sources. One the Timer 0 starts counting, it will count from the current contents in the counter to FFH. Once an overflow occurs, the counter is reloaded from a preload register, and generates an interrupt request flag (T0F; bit 2 of INTCH). To enable the counting operation, the timer On bit (TON; bit 4 of TMR0C) should be set to 1. For proper operation, bit 7 of TMR0C should be set to 1 and bit 3, bit 6 should be set to 0. There are two registers related to the Timer Counter1; TMR1L(10H), TMR1C(11H). The Timer Counter 1 operates in the same manner as Timer Counter 0. TMR0C/TMR1C B2 0 0 0 0 1 1 1 1 B1 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1 fOSC/16 fOSC/32 fOSC/64 fOSC/128 fOSC/256 fOSC/512 fOSC/1024 fOSC/2048 T0F TMR0C Bit 4 to enable/disable timer counting (1=enable; 0=disable) TMR0C Bit 3, always write 0. TMR0C Bit 5, always write 0. TMR0C Bit 6, always write 0. TMR0C Bit 7, always write 1.
D a ta B u s T im e r 0 /1 P r e lo a d R e g is te r R e lo a d
fO
SC
/8
8 -s ta g e P r e s c a le r T0F TON
T im e r 0 /1
O v e r flo w
Timer 0/1 Input/Output Ports There are 8 bidirectional input/output lines labeled PA, which are mapped to the data memory of [12H] respectively. All these I/O ports can be used for input and output operations. For input operation, these ports are non-latching, that is, the inputs must be ready at the T2 rising edge of instruction MOV A,[m] (m=12H). For output operation, all data is latched and remains unchanged until the output latch is rewritten. Each I/O line has its own control register (PAC) to control the input/output configuration. With this control register, CMOS output or Schmitt trigger input with or without pull-high resistor (mask option) structures can be reconfigured dynamically under software control. To function as an input, the corresponding latch of the control register must write a 1. The pull-high resistance will exhibit automatically if the pull-high option is selected. The input source also depends on the control register. If the control register bit is 1, input will read the pad state. If the control register bit is 0, the contents of the latches will move to the internal bus. The latter is possible in read-modify-write instruction. For output function, CMOS is the only configuration. These control registers are mapped to locations 13H.
D a ta B u s D W r ite C o n tr o l R e g is te r C h ip R e s e t R e a d C o n tr o l R e g is te r
Q CK S Q V
V
DD
DD
W eak P u ll- u p M a s k O p tio n
D W r ite I/O CK S Q
Q
PA0~PA7
M R e a d I/O S y s te m W a k e -U p M a s k O p tio n U
X
Input/Output Ports Rev. 1.10 15 March 12, 2007
HT36A4
After a chip reset, these input/output lines remain at high levels or floating (mask option). Each bit of these input/output latches can be set or cleared by the SET [m].i or CLR [m].i (m=12H) instruction. Some instructions first input data and then follow the output operations. For example, the SET [m].i, CLR [m].i, CPL [m] and CPLA [m] instructions read the entire port states into the CPU, execute the defined operations (bit-operation), and then write the results back to the latches or the accumulator. Each line of port A has the capability to wake-up the device.
8 Channel Wavetable Synthesizer
Wavetable Function Memory Mapping Special Register for Wavetable Synthesizer RAM 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 2AH VR7 VR6 VR5 VR4 VR3 VR2 ST7 WBS RE7 RE6 RE5 RE4 RE3 RE2 ST6 ST5 ST4 ST3 VM BL3 FR7 FR BL2 FR6 BL1 FR5 BL0 FR4 FR11 FR3 CH2 FR10 FR2 ST10 ST2 B7 DA15 DA7 B6 DA14 DA6 B5 DA13 DA5 B4 DA12 DA4 B3 DA11 DA3 B2 DA10 DA2 B1 DA9 DA1 DAON CH1 FR9 FR1 ST9 ST1 RE9 RE1 VR9 VR1 B0 DA8 DA0 SELW CH0 FR8 FR0 ST8 ST0 RE8 RE0 VR8 VR0
Wavetable Function Register Table Register Name 1DH 1EH Register Function DAC high byte (no default value) DAC low byte (no default value) DAON=1: DAC ON DAON=0: DAC OFF (default) SELW=1: DAC data from wavetable SELW=0: DAC data from MCU Channel Number Selection Change Parameter Selection Block Number Selection Frequency Number Selection VM BL3 FR BL2 BL1 BL0 FR11 FR7 FR6 FR5 FR4 FR3 FR10 FR2 ST10 ST7 WBS RE9 RE7 RE6 RE5 RE4 RE3 RE2 RE1 VR9 VR7 VR6 VR5 VR4 VR3 VR2 VR1 RE8 RE0 VR8 VR0 ST6 ST5 ST4 ST3 ST2 FR9 FR1 ST9 ST1 FR8 FR0 ST8 ST0 CH2 B7 B6 B5 DA13 DA5 B4 DA12 DA4 B3 DA11 DA3 B2 DA10 DA2 B1 DA9 DA1 B0 DA8 DA0
DA15 DA14 DA7 DA6
1FH
DAON SELW
20H 20H 21H 21H 22H 23H 24H 25H 25H 26H 27H 2AH
CH1
CH0
Start Address Selection Waveform Format Selection Repeat Number Selection
Volume Controller
Rev. 1.10
16
March 12, 2007
HT36A4
* CH[2~0] channel number selection * Waveform format definition
The HT36A4 has a built-in 8 output channels and CH[2~0] is used to define which channel is selected. When this register is written to, the wavetable synthesizer will automatically output the dedicated PCM code. So this register is also used as a start playing key and it has to be written to after all the other wavetable function registers are already defined.
* Change parameter selection
The HT36A4 accepts two waveform formats to ensure a more economical data space. WBS is used to define the sample format of each PCM code.

WBS=0 means the sample format is 8-bit WBS=1 means the sample format is 12-bit
The 12-bit sample format allocates location to each sample data. Please refer to the waveform format statement as shown below.
8 - B it 1B 2B 3B 4B 5B 6B 7B 8B
These two bits, VM and FR, are used to define which register will be updated on this selected channel. There are two modes that can be selected to reduce the process of setting the register. Please refer to the statements of the following table: VM 0 0 1 FR 0 1 0 Function Update all the parameter Only update the frequency number Only update the volume
A s a m p lin g d a ta c o d e ; B m e a n s o n e d a ta b y te . 1 2 - B it 1H 1M 1L 2L 2H 2M 3H 3M 3L
A s a m p lin g d a ta c o d e N o te : " 1 H " H ig h N ib b le " 1 M " M id d le N ib b le " 1 L " L o w N ib b le
* Output frequency definition
Waveform Format
* Repeat number definition
The data on BL[3~0] and FR[11~0] are used to define the output speed of the PCM file, i.e. it can be used to generate the tone scale. When the FR[11:0] is 800H and BL[3:0] is 6H, each sample data of the PCM code will be sent out sequentially. When the fOSC is 6.4MHz, the formula of a tone frequency is: 25kHz FR [11~ 0] (17 - BL [3~0]) fOUT= fRECORD SR 2 where fOUT is the output signal frequency, fRECORD and SR is the frequency and sampling rate on the sample code, respectively. So if a voice code of C3 has been recorded which has the fRECORD of 261Hz and the SR of 11025Hz, the tone frequency (fOUT) of G3: fOUT=98Hz. Can be obtained by using the fomula: 25kHz FR[11 ~ 0] 98Hz= 261Hz 11025Hz 2 (17 - BL [3~0]) A pair of the values FR[11~0] and BL[3~0] can be determined when the fOSC is 6.4MHz.
* Start address definition
The repeat number is used to define the address which is the repeat point of the sample. When the repeat number is defined, it will be output from the start code to the end code once and always output the range between the repeat address to the end code (80H) until the volume become close. The RE[9~0] is used to calculate the repeat address of the PCM code. The process for setting the RE[9~0] is to write the 2s complement of the repeat length to RE[9~0], with the highest carry ignored. The HT36A4 will get the repeat address by adding the RE[9~0] to the address of the end code, then jump to the address to repeat this range.
* Volume control
The HT36A4 provides the volume control independently. The volume are controlled by VR[9~0] respectively. The chip provides 1024 levels of controllable volume, the 000H is the maximum and 3FFH is the minimum output volume.
* The PCM code definition
The HT36A4 provides two address types for extended use, one is the program ROM address which is program counter corresponding with PF value, the other is the start address of the PCM code. The ST[10~0] is used to define the start address of each PCM code and reads the waveform data from this location. The HT36A4 provides 16 input data lines from WA[15~0], the ST[10~0] is used to locate the major 11 bits i.e. WA[15~5] and the undefined data from WA[4~0] is always set as 00000b. In other words, the WA[15~0]=ST[10~0]25. So each PCM code has to be located at a multiple of 32. Otherwise, the PCM code will not be read out correctly because it has a wrong start code.
The HT36A4 can only solve the voice format of the signed 8-bit raw PCM. And the MCU will take the voice code 80H as the end code. So each PCM code section must be ended with the end code 80H.
Rev. 1.10
17
March 12, 2007
HT36A4
Mask Option No. 1 2 3 4 5 Mask Option WDT source CLRWDT times Wake-up Pull-High OSC mode Function On-chip RC/Instruction clock/ disable WDT One time, two times (CLR WDT1/WDT2) PA PA input Crystal or Resistor type
Application Circuits
V
DD
10W VDD OSC1 OSC2 PA0~PA7 47mF V 100kW RES 0 .1 m F 0 6!$) " VSSA VSS 10mF
DD
VDDA
47mF
0 .1 m F
V
DD
AUD 20kW
0 .1 m F 2
IN
8 VDD 1 VSS 4 5 CE 06& 8%!!
OUTN 7 OUTP SPK 8W
V re f 3
V
DD
10W VDD OSC1 8M H z OSC2 V 100kW RES 0 .1 m F 0 6!$) " VSSA VSS
DD
VDDA
47mF
0 .1 m F
PA0~PA7
V
DD
AUD
1kW 750W
SPK 8W
Rev. 1.10
18
March 12, 2007
HT36A4
Instruction Set Summary
Mnemonic Arithmetic ADD A,[m] ADDM A,[m] ADD A,x ADC A,[m] ADCM A,[m] SUB A,x SUB A,[m] SUBM A,[m] SBC A,[m] SBCM A,[m] DAA [m] Add data memory to ACC Add ACC to data memory Add immediate data to ACC Add data memory to ACC with carry Add ACC to data memory with carry Subtract immediate data from ACC Subtract data memory from ACC Subtract data memory from ACC with result in data memory Subtract data memory from ACC with carry Subtract data memory from ACC with carry and result in data memory Decimal adjust ACC for addition with result in data memory 1 1(1) 1 1 1(1) 1 1 1(1) 1 1(1) 1(1) Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV C Description Instruction Cycle Flag Affected
Logic Operation AND A,[m] OR A,[m] XOR A,[m] ANDM A,[m] ORM A,[m] XORM A,[m] AND A,x OR A,x XOR A,x CPL [m] CPLA [m] AND data memory to ACC OR data memory to ACC Exclusive-OR data memory to ACC AND ACC to data memory OR ACC to data memory Exclusive-OR ACC to data memory AND immediate data to ACC OR immediate data to ACC Exclusive-OR immediate data to ACC Complement data memory Complement data memory with result in ACC 1 1 1 1(1) 1(1) 1(1) 1 1 1 1(1) 1 Z Z Z Z Z Z Z Z Z Z Z
Increment & Decrement INCA [m] INC [m] DECA [m] DEC [m] Rotate RRA [m] RR [m] RRCA [m] RRC [m] RLA [m] RL [m] RLCA [m] RLC [m] Data Move MOV A,[m] MOV [m],A MOV A,x Bit Operation CLR [m].i SET [m].i Clear bit of data memory Set bit of data memory 1(1) 1(1) None None Move data memory to ACC Move ACC to data memory Move immediate data to ACC 1 1(1) 1 None None None Rotate data memory right with result in ACC Rotate data memory right Rotate data memory right through carry with result in ACC Rotate data memory right through carry Rotate data memory left with result in ACC Rotate data memory left Rotate data memory left through carry with result in ACC Rotate data memory left through carry 1 1(1) 1 1(1) 1 1(1) 1 1(1) None None C C None None C C Increment data memory with result in ACC Increment data memory Decrement data memory with result in ACC Decrement data memory 1 1(1) 1 1(1) Z Z Z Z
Rev. 1.10
19
March 12, 2007
HT36A4
Mnemonic Branch JMP addr SZ [m] SZA [m] SZ [m].i SNZ [m].i SIZ [m] SDZ [m] SIZA [m] SDZA [m] CALL addr RET RET A,x RETI Table Read TABRDC [m] TABRDL [m] Miscellaneous NOP CLR [m] SET [m] CLR WDT CLR WDT1 CLR WDT2 SWAP [m] SWAPA [m] HALT Note: No operation Clear data memory Set data memory Clear Watchdog Timer Pre-clear Watchdog Timer Pre-clear Watchdog Timer Swap nibbles of data memory Swap nibbles of data memory with result in ACC Enter power down mode 1 1(1) 1(1) 1 1 1 1(1) 1 1 None None None TO,PDF TO(4),PDF(4) TO(4),PDF(4) None None TO,PDF Read ROM code (current page) to data memory and TBLH Read ROM code (last page) to data memory and TBLH 2(1) 2(1) None None Jump unconditionally Skip if data memory is zero Skip if data memory is zero with data movement to ACC Skip if bit i of data memory is zero Skip if bit i of data memory is not zero Skip if increment data memory is zero Skip if decrement data memory is zero Skip if increment data memory is zero with result in ACC Skip if decrement data memory is zero with result in ACC Subroutine call Return from subroutine Return from subroutine and load immediate data to ACC Return from interrupt 2 1(2) 1(2) 1(2) 1(2) 1(3) 1(3) 1(2) 1(2) 2 2 2 2 None None None None None None None None None None None None None Description Instruction Cycle Flag Affected
x: Immediate data m: Data memory address A: Accumulator i: 0~7 number of bits addr: Program memory address O: Flag is affected -: Flag is not affected
(1)
: If a loading to the PCL register occurs, the execution cycle of instructions will be delayed for one more cycle (four system clocks). : If a skipping to the next instruction occurs, the execution cycle of instructions will be delayed for one more cycle (four system clocks). Otherwise the original instruction cycle is unchanged. : and (2)
(2)
(3) (1) (4)
: The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the CLR WDT1 or CLR WDT2 instruction, the TO and PDF are cleared. Otherwise the TO and PDF flags remain unchanged.
Rev. 1.10
20
March 12, 2007
HT36A4
Instruction Definition
ADC A,[m] Description Operation Affected flag(s) TO 3/4 ADCM A,[m] Description Operation Affected flag(s) TO 3/4 ADD A,[m] Description Operation Affected flag(s) TO 3/4 ADD A,x Description Operation Affected flag(s) TO 3/4 ADDM A,[m] Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O Add data memory and carry to the accumulator The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the accumulator. ACC ACC+[m]+C
Add the accumulator and carry to data memory The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the specified data memory. [m] ACC+[m]+C
Add data memory to the accumulator The contents of the specified data memory and the accumulator are added. The result is stored in the accumulator. ACC ACC+[m]
Add immediate data to the accumulator The contents of the accumulator and the specified data are added, leaving the result in the accumulator. ACC ACC+x
Add the accumulator to the data memory The contents of the specified data memory and the accumulator are added. The result is stored in the data memory. [m] ACC+[m]
Rev. 1.10
21
March 12, 2007
HT36A4
AND A,[m] Description Operation Affected flag(s) TO 3/4 AND A,x Description Operation Affected flag(s) TO 3/4 ANDM A,[m] Description Operation Affected flag(s) TO 3/4 CALL addr Description PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 Logical AND accumulator with data memory Data in the accumulator and the specified data memory perform a bitwise logical_AND operation. The result is stored in the accumulator. ACC ACC AND [m]
Logical AND immediate data to the accumulator Data in the accumulator and the specified data perform a bitwise logical_AND operation. The result is stored in the accumulator. ACC ACC AND x
Logical AND data memory with the accumulator Data in the specified data memory and the accumulator perform a bitwise logical_AND operation. The result is stored in the data memory. [m] ACC AND [m]
Subroutine call The instruction unconditionally calls a subroutine located at the indicated address. The program counter increments once to obtain the address of the next instruction, and pushes this onto the stack. The indicated address is then loaded. Program execution continues with the instruction at this address. Stack Program Counter+1 Program Counter addr TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation
Affected flag(s)
CLR [m] Description Operation Affected flag(s)
Clear data memory The contents of the specified data memory are cleared to 0. [m] 00H TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Rev. 1.10
22
March 12, 2007
HT36A4
CLR [m].i Description Operation Affected flag(s) TO 3/4 CLR WDT Description Operation PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Clear bit of data memory The bit i of the specified data memory is cleared to 0. [m].i 0
Clear Watchdog Timer The WDT is cleared (clears the WDT). The power down bit (PDF) and time-out bit (TO) are cleared. WDT 00H PDF and TO 0 TO 0 PDF 0 OV 3/4 Z 3/4 AC 3/4 C 3/4
Affected flag(s)
CLR WDT1 Description
Preclear Watchdog Timer Together with CLR WDT2, clears the WDT. PDF and TO are also cleared. Only execution of this instruction without the other preclear instruction just sets the indicated flag which implies this instruction has been executed and the TO and PDF flags remain unchanged. WDT 00H* PDF and TO 0* TO 0* PDF 0* OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation
Affected flag(s)
CLR WDT2 Description
Preclear Watchdog Timer Together with CLR WDT1, clears the WDT. PDF and TO are also cleared. Only execution of this instruction without the other preclear instruction, sets the indicated flag which implies this instruction has been executed and the TO and PDF flags remain unchanged. WDT 00H* PDF and TO 0* TO 0* PDF 0* OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation
Affected flag(s)
CPL [m] Description Operation Affected flag(s)
Complement data memory Each bit of the specified data memory is logically complemented (1s complement). Bits which previously contained a 1 are changed to 0 and vice-versa. [m] [m] TO 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4
Rev. 1.10
23
March 12, 2007
HT36A4
CPLA [m] Description Complement data memory and place result in the accumulator Each bit of the specified data memory is logically complemented (1s complement). Bits which previously contained a 1 are changed to 0 and vice-versa. The complemented result is stored in the accumulator and the contents of the data memory remain unchanged. ACC [m] TO 3/4 DAA [m] Description PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4
Operation Affected flag(s)
Decimal-Adjust accumulator for addition The accumulator value is adjusted to the BCD (Binary Coded Decimal) code. The accumulator is divided into two nibbles. Each nibble is adjusted to the BCD code and an internal carry (AC1) will be done if the low nibble of the accumulator is greater than 9. The BCD adjustment is done by adding 6 to the original value if the original value is greater than 9 or a carry (AC or C) is set; otherwise the original value remains unchanged. The result is stored in the data memory and only the carry flag (C) may be affected. If ACC.3~ACC.0 >9 or AC=1 then [m].3~[m].0 (ACC.3~ACC.0)+6, AC1=AC else [m].3~[m].0 (ACC.3~ACC.0), AC1=0 and If ACC.7~ACC.4+AC1 >9 or C=1 then [m].7~[m].4 ACC.7~ACC.4+6+AC1,C=1 else [m].7~[m].4 ACC.7~ACC.4+AC1,C=C TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Operation
Affected flag(s)
DEC [m] Description Operation Affected flag(s)
Decrement data memory Data in the specified data memory is decremented by 1. [m] [m]-1 TO 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4
DECA [m] Description Operation Affected flag(s)
Decrement data memory and place result in the accumulator Data in the specified data memory is decremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged. ACC [m]-1 TO 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4
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HALT Description Enter power down mode This instruction stops program execution and turns off the system clock. The contents of the RAM and registers are retained. The WDT and prescaler are cleared. The power down bit (PDF) is set and the WDT time-out bit (TO) is cleared. Program Counter Program Counter+1 PDF 1 TO 0 TO 0 INC [m] Description Operation Affected flag(s) TO 3/4 INCA [m] Description Operation Affected flag(s) TO 3/4 JMP addr Description Operation Affected flag(s) TO 3/4 MOV A,[m] Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Directly jump The program counter are replaced with the directly-specified address unconditionally, and control is passed to this destination. Program Counter addr PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 1 OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation
Affected flag(s)
Increment data memory Data in the specified data memory is incremented by 1 [m] [m]+1
Increment data memory and place result in the accumulator Data in the specified data memory is incremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged. ACC [m]+1
Move data memory to the accumulator The contents of the specified data memory are copied to the accumulator. ACC [m]
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MOV A,x Description Operation Affected flag(s) TO 3/4 MOV [m],A Description Operation Affected flag(s) TO 3/4 NOP Description Operation Affected flag(s) TO 3/4 OR A,[m] Description Operation Affected flag(s) TO 3/4 OR A,x Description Operation Affected flag(s) TO 3/4 ORM A,[m] Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 No operation No operation is performed. Execution continues with the next instruction. Program Counter Program Counter+1 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Move immediate data to the accumulator The 8-bit data specified by the code is loaded into the accumulator. ACC x
Move the accumulator to data memory The contents of the accumulator are copied to the specified data memory (one of the data memories). [m] ACC
Logical OR accumulator with data memory Data in the accumulator and the specified data memory (one of the data memories) perform a bitwise logical_OR operation. The result is stored in the accumulator. ACC ACC OR [m]
Logical OR immediate data to the accumulator Data in the accumulator and the specified data perform a bitwise logical_OR operation. The result is stored in the accumulator. ACC ACC OR x
Logical OR data memory with the accumulator Data in the data memory (one of the data memories) and the accumulator perform a bitwise logical_OR operation. The result is stored in the data memory. [m] ACC OR [m]
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RET Description Operation Affected flag(s) TO 3/4 RET A,x Description Operation PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Return from subroutine The program counter is restored from the stack. This is a 2-cycle instruction. Program Counter Stack
Return and place immediate data in the accumulator The program counter is restored from the stack and the accumulator loaded with the specified 8-bit immediate data. Program Counter Stack ACC x TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Affected flag(s)
RETI Description Operation
Return from interrupt The program counter is restored from the stack, and interrupts are enabled by setting the EMI bit. EMI is the enable master (global) interrupt bit. Program Counter Stack EMI 1 TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Affected flag(s)
RL [m] Description Operation
Rotate data memory left The contents of the specified data memory are rotated 1 bit left with bit 7 rotated into bit 0. [m].(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) [m].0 [m].7 TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Affected flag(s)
RLA [m] Description Operation
Rotate data memory left and place result in the accumulator Data in the specified data memory is rotated 1 bit left with bit 7 rotated into bit 0, leaving the rotated result in the accumulator. The contents of the data memory remain unchanged. ACC.(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) ACC.0 [m].7 TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Affected flag(s)
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RLC [m] Description Operation Rotate data memory left through carry The contents of the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the carry bit; the original carry flag is rotated into the bit 0 position. [m].(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) [m].0 C C [m].7 TO 3/4 RLCA [m] Description PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Affected flag(s)
Rotate left through carry and place result in the accumulator Data in the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the carry bit and the original carry flag is rotated into bit 0 position. The rotated result is stored in the accumulator but the contents of the data memory remain unchanged. ACC.(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) ACC.0 C C [m].7 TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Operation
Affected flag(s)
RR [m] Description Operation
Rotate data memory right The contents of the specified data memory are rotated 1 bit right with bit 0 rotated to bit 7. [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m].7 [m].0 TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Affected flag(s)
RRA [m] Description Operation
Rotate right and place result in the accumulator Data in the specified data memory is rotated 1 bit right with bit 0 rotated into bit 7, leaving the rotated result in the accumulator. The contents of the data memory remain unchanged. ACC.(i) [m].(i+1); [m].i:bit i of the data memory (i=0~6) ACC.7 [m].0 TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Affected flag(s)
RRC [m] Description Operation
Rotate data memory right through carry The contents of the specified data memory and the carry flag are together rotated 1 bit right. Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position. [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m].7 C C [m].0 TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Affected flag(s)
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RRCA [m] Description Rotate right through carry and place result in the accumulator Data of the specified data memory and the carry flag are rotated 1 bit right. Bit 0 replaces the carry bit and the original carry flag is rotated into the bit 7 position. The rotated result is stored in the accumulator. The contents of the data memory remain unchanged. ACC.i [m].(i+1); [m].i:bit i of the data memory (i=0~6) ACC.7 C C [m].0 TO 3/4 SBC A,[m] Description Operation Affected flag(s) TO 3/4 SBCM A,[m] Description Operation Affected flag(s) TO 3/4 SDZ [m] Description PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Operation
Affected flag(s)
Subtract data memory and carry from the accumulator The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the accumulator. ACC ACC+[m]+C
Subtract data memory and carry from the accumulator The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the data memory. [m] ACC+[m]+C
Skip if decrement data memory is 0 The contents of the specified data memory are decremented by 1. If the result is 0, the next instruction is skipped. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]-1)=0, [m] ([m]-1) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation Affected flag(s)
SDZA [m] Description
Decrement data memory and place result in ACC, skip if 0 The contents of the specified data memory are decremented by 1. If the result is 0, the next instruction is skipped. The result is stored in the accumulator but the data memory remains unchanged. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]-1)=0, ACC ([m]-1) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation Affected flag(s)
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SET [m] Description Operation Affected flag(s) TO 3/4 SET [m]. i Description Operation Affected flag(s) TO 3/4 SIZ [m] Description PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Set data memory Each bit of the specified data memory is set to 1. [m] FFH
Set bit of data memory Bit i of the specified data memory is set to 1. [m].i 1
Skip if increment data memory is 0 The contents of the specified data memory are incremented by 1. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]+1)=0, [m] ([m]+1) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation Affected flag(s)
SIZA [m] Description
Increment data memory and place result in ACC, skip if 0 The contents of the specified data memory are incremented by 1. If the result is 0, the next instruction is skipped and the result is stored in the accumulator. The data memory remains unchanged. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]+1)=0, ACC ([m]+1) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation Affected flag(s)
SNZ [m].i Description
Skip if bit i of the data memory is not 0 If bit i of the specified data memory is not 0, the next instruction is skipped. If bit i of the data memory is not 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m].i0
Operation Affected flag(s)
TO 3/4
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
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SUB A,[m] Description Operation Affected flag(s) TO 3/4 SUBM A,[m] Description Operation Affected flag(s) TO 3/4 SUB A,x Description Operation Affected flag(s) TO 3/4 SWAP [m] Description Operation Affected flag(s) TO 3/4 SWAPA [m] Description Operation PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O Subtract data memory from the accumulator The specified data memory is subtracted from the contents of the accumulator, leaving the result in the accumulator. ACC ACC+[m]+1
Subtract data memory from the accumulator The specified data memory is subtracted from the contents of the accumulator, leaving the result in the data memory. [m] ACC+[m]+1
Subtract immediate data from the accumulator The immediate data specified by the code is subtracted from the contents of the accumulator, leaving the result in the accumulator. ACC ACC+x+1
Swap nibbles within the data memory The low-order and high-order nibbles of the specified data memory (1 of the data memories) are interchanged. [m].3~[m].0 [m].7~[m].4
Swap data memory and place result in the accumulator The low-order and high-order nibbles of the specified data memory are interchanged, writing the result to the accumulator. The contents of the data memory remain unchanged. ACC.3~ACC.0 [m].7~[m].4 ACC.7~ACC.4 [m].3~[m].0 TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Affected flag(s)
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SZ [m] Description Skip if data memory is 0 If the contents of the specified data memory are 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m]=0
Operation Affected flag(s)
TO 3/4 SZA [m] Description
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Move data memory to ACC, skip if 0 The contents of the specified data memory are copied to the accumulator. If the contents is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m]=0
Operation Affected flag(s)
TO 3/4 SZ [m].i Description
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Skip if bit i of the data memory is 0 If bit i of the specified data memory is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m].i=0
Operation Affected flag(s)
TO 3/4 TABRDC [m] Description Operation
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Move the ROM code (current page) to TBLH and data memory The low byte of ROM code (current page) addressed by the table pointer (TBLP) is moved to the specified data memory and the high byte transferred to TBLH directly. [m] ROM code (low byte) TBLH ROM code (high byte) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Affected flag(s)
TABRDL [m] Description Operation
Move the ROM code (last page) to TBLH and data memory The low byte of ROM code (last page) addressed by the table pointer (TBLP) is moved to the data memory and the high byte transferred to TBLH directly. [m] ROM code (low byte) TBLH ROM code (high byte) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Affected flag(s)
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XOR A,[m] Description Operation Affected flag(s) TO 3/4 XORM A,[m] Description Operation Affected flag(s) TO 3/4 XOR A,x Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 Logical XOR accumulator with data memory Data in the accumulator and the indicated data memory perform a bitwise logical Exclusive_OR operation and the result is stored in the accumulator. ACC ACC XOR [m]
Logical XOR data memory with the accumulator Data in the indicated data memory and the accumulator perform a bitwise logical Exclusive_OR operation. The result is stored in the data memory. The 0 flag is affected. [m] ACC XOR [m]
Logical XOR immediate data to the accumulator Data in the accumulator and the specified data perform a bitwise logical Exclusive_OR operation. The result is stored in the accumulator. The 0 flag is affected. ACC ACC XOR x
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HT36A4
Package Information
16-pin DIP (300mil) Outline Dimensions
A 16 B 1 9 8
H C D E F G
a
I
Symbol A B C D E F G H I a
Dimensions in mil Min. 745 240 125 125 16 50 3/4 295 335 0 Nom. 3/4 3/4 3/4 3/4 3/4 3/4 100 3/4 3/4 3/4 Max. 775 260 135 145 20 70 3/4 315 375 15
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HT36A4
16-pin SOP (300mil) Outline Dimensions
16 9 A
B 1 8 C C' G H
D E F
a
Symbol A B C C D E F G H a
Dimensions in mil Min. 394 290 14 390 92 3/4 4 32 4 0 Nom. 3/4 3/4 3/4 3/4 3/4 50 3/4 3/4 3/4 3/4 Max. 419 300 20 413 104 3/4 3/4 38 12 10
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Product Tape and Reel Specifications
Reel Dimensions
T2 D
A
B
C
T1
SOP 16W (300mil) Symbol A B C D T1 T2 Description Reel Outer Diameter Reel Inner Diameter Spindle Hole Diameter Key Slit Width Space Between Flange Reel Thickness Dimensions in mm 3301 621.5 130.5 -0.2 20.5 16.8+0.3 -0.2 22.20.2
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Carrier Tape Dimensions
D
E F W C
P0
P1
t
B0
D1
P
K0 A0
SOP 16W (300mil) Symbol W P E F D D1 P0 P1 A0 B0 K0 t C Description Carrier Tape Width Cavity Pitch Perforation Position Cavity to Perforation (Width Direction) Perforation Diameter Cavity Hole Diameter Perforation Pitch Cavity to Perforation (Length Direction) Cavity Length Cavity Width Cavity Depth Carrier Tape Thickness Cover Tape Width Dimensions in mm 160.2 120.1 1.750.1 7.50.1 1.5+0.1 1.5+0.25 40.1 20.1 10.90.1 10.80.1 30.1 0.30.05 13.3
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Holtek Semiconductor Inc. (Headquarters) No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 http://www.holtek.com.tw Holtek Semiconductor Inc. (Taipei Sales Office) 4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan Tel: 886-2-2655-7070 Fax: 886-2-2655-7373 Fax: 886-2-2655-7383 (International sales hotline) Holtek Semiconductor Inc. (Shanghai Sales Office) 7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China 200233 Tel: 86-21-6485-5560 Fax: 86-21-6485-0313 http://www.holtek.com.cn Holtek Semiconductor Inc. (Shenzhen Sales Office) 5/F, Unit A, Productivity Building, Cross of Science M 3rd Road and Gaoxin M 2nd Road, Science Park, Nanshan District, Shenzhen, China 518057 Tel: 86-755-8616-9908, 86-755-8616-9308 Fax: 86-755-8616-9722 Holtek Semiconductor Inc. (Beijing Sales Office) Suite 1721, Jinyu Tower, A129 West Xuan Wu Men Street, Xicheng District, Beijing, China 100031 Tel: 86-10-6641-0030, 86-10-6641-7751, 86-10-6641-7752 Fax: 86-10-6641-0125 Holtek Semiconductor Inc. (Chengdu Sales Office) 709, Building 3, Champagne Plaza, No.97 Dongda Street, Chengdu, Sichuan, China 610016 Tel: 86-28-6653-6590 Fax: 86-28-6653-6591 Holtek Semiconductor (USA), Inc. (North America Sales Office) 46729 Fremont Blvd., Fremont, CA 94538 Tel: 1-510-252-9880 Fax: 1-510-252-9885 http://www.holmate.com
Copyright O 2007 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holteks products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw.
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